In recent years, with the reduction in size and weight for electronic devices, laminated ceramic capacitors have been used widely which are small in size and capable of acquiring high capacitance. These laminated ceramic capacitors have, for example, as shown in FIG. 2, a structure including: a laminated body 10 including a plurality of dielectric ceramic layers 11 stacked, and a plurality of internal electrodes 12 provided at a plurality of interfaces between the dielectric ceramic layers 11; and a pair of external electrodes 13a, 13b provided on both end surfaces of the laminated body 10 so as to be brought into electrical continuity with the internal electrodes 12 alternately exposed at the opposite end surfaces.
Furthermore, in these laminated ceramic capacitors, dielectric ceramic materials which have a high dielectric constant and contain, as their main constituent, a perovskite-type compound containing Ba, Ti, etc. have been used widely as the material constituting the dielectric ceramic layers.
Furthermore, dielectric ceramic compositions as described in Patent Document 1 have been proposed as such dielectric ceramic materials.
This dielectric ceramic composition contains, as its main constituent, a composition represented by a general formula: n(BaOx—SrOy—CaOz) (ZrmTi1-m)O2 (where x+y+z=1, x, y, z, m, and n represent molar ratios) in which x, y, and z are, in terms of molar ratio, in the composition ranges shown in Table 1 of Patent Document 1 where a, b, c, d, and e are surrounded by straight lines, and m and n are in the ranges of m≧0.95 and 0.8≧n≧1.04, and contains as additives, 0.1 to 0.7 wt % of Mn3O4, 0.5 to 3.0 wt % of BaSiO3, 0.01 to 0.07 wt % of V2O5, and further 0.05 to 0.30 wt % of Al2O3 added with respect to 100 wt % of the main constituent.
However, in the case of the conventional dielectric ceramic composition mentioned above, because grain growth of crystal grains by firing is likely to be promoted rapidly, there is a problem that in particular, in such a thin-layer region having a thickness of the dielectric ceramic layer (the thickness of a dielectric ceramic layer sandwiched between internal electrodes for the formation of capacitance) of 3 μm or less, the grain sizes (grain sizes) of crystal grains with respect to the thickness of the dielectric ceramic layer are excessively increased to not only increase the initial short circuit ratio, but also increase the time degradation in insulation resistance in a high-temperature load test, thereby shortening the high-temperature load life.
Patent Document 1: Japanese Patent Application Laid-Open No. 2001-294481